One-time-programmable (“OTP”) memory elements are used in integrated circuits (“IC”) to provide non-volatile memory (“NVM”). Data in NVM are not lost when the IC is turned off. NVM allows an IC manufacturer to store lot number and security data on the IC, for example, and is useful in many other applications. Devices commonly known as fuses and anti-fuses are examples of OTP memory elements.
Unfortunately, the types of fuses and anti-fuses commonly used in memory IC, such as read-only memory (“ROM”) ICs typically use processes and materials that are not used in a standard complementary metal-oxide-semiconductor (“CMOS”) ICs. Electronically programmable fuses (“E-fuses”) have been developed that can be incorporated in an IC using typically CMOS fabrication techniques.
FIG. 1A is a plan view of an E-fuse element 100. The E-fuse 100 has a fuse link 102 between a first fuse terminal (anode) 104 and a second fuse terminal (cathode) 106. The anode, fuse link, and cathode are typically polysilicon or silicided polysilicon formed entirely on relatively thick field oxide or isolation oxide. Contacts (not shown) provide electrical terminals to the anode and cathode. The fuse link has a fuse link length FLL and a fuse link width FLW. The fuse link has a relatively small cross section, which is essentially defined by the thickness of the material in which the fuse link is formed in and by the fuse link width. The fuse link width FLW is often the critical dimension (e.g., minimum polysilicon dimension) of the technology used to fabricate the IC. The small cross section of the fuse link results in Joule heating of the link during programming to convert the E-fuse to a high-resistance state.
The terms “anode” and “cathode” are used for purposes of convenient discussion. Whether a terminal of an E-fuse operates as an anode or a cathode depends upon how the programming current is applied. Programming of the E-fuse can be facilitated by the physical layout. For example, the cathode 106 is larger than the fuse link 102, which generates localized Joule heating in the fuse link during programming.
During programming, current is applied through the fuse link for a specified period. The programming current heats up the fuse link more than the adjacent areas due to current crowding and differences in heat dissipation, creating a temperature gradient. The temperature gradient and the carrier flux causes electro- and stress-migration to take place and drive material (e.g., silicide, dopant, and polysilicon) away from the fuse link, and in some cases physically separates (“blows”) portions of the fuse link. Programming generally converts the E-fuse from an original (low) resistance to a programmed (high) resistance.
FIG. 1B is a side view of the E-fuse 100 of FIG. 1A. The E-fuse 100 is fabricated from a layer of link material 101 that is deposited on the IC substrate and patterned using photolithographic techniques to define the anode 104, cathode 106, and fuse link 102. The fuse link 102 has a fuse link thickness FLT that is essentially the thickness of the layer of link material 101. The E-fuse is on field oxide 108 that is formed on semiconductor material 110 (e.g., silicon).
FIG. 1C shows a prior art circuit 120 for reading the data value of an E-fuse 122 (i.e., whether the E-fuse is in its original state or a programmed state). A first logic state (e.g., a logical “0”) is typically assigned to an unprogrammed, low-resistance (typically about 100 Ohms) fuse state, and a second logic state (e.g., a logical “1”) to the programmed, high-resistance (typically between about 2,000 Ohms and about 8,000 Ohms) fuse state. The change in resistance is sensed (read) by a sensing circuit to produce a data bit.
When a READ enable signal (READEN) is applied, transistors TN1, TN2 and TN3 are turned on. Transistor TP1 is on, and READ current IREAD flows through transistors TP1, TN1, TN2, and TN3 (which will be referred to as a sense circuit for purposes of discussion), and through the E-fuse 122. If the E-fuse 122 is in a pristine (i.e., the unprogrammed low-resistance) state, the voltage at trip node 124 is relatively low. If the E-fuse has been programmed to a high-resistance state, the voltage at trip node 124 is higher. The inverter 126 is designed to trip from one data value to another. In other words, the inverter 126 is designed to transition from a first output state (e.g., digital value 1) to a second output state (e.g., digital value 0) at a selected input voltage. The input voltage at which the inverter 126 trips is selected to be between the voltage expected at trip node 124 when the E-fuse is in a pristine state, and the voltage expected at trip node 124 when the E-fuse has been programmed.
The output of inverter 126 is coupled to a pass gate 128 that reads the data out of the inverter, and then to an inverting latch 130. The second inverter 132 in the output path flips the data value from the first inverter 126 back to the data value sensed at the input (node 124) of the first inverter 126. Thus, the data value stored in the E-fuse 122 is provided to the output 134 of the sense circuit 120 as output data DOUT. The portion of the circuit 100 between the trip node 124 and data output 134 will be referred to as the output path or latched output path for purposes of discussion.
Unfortunately, fabrication process variations, programming process variations, and operating temperature variations can affect the accuracy of the trip point, and thus the fidelity of the output data DOUT. For example, the post-programming resistance can be between a few thousand Ohms and several thousand Ohms for some E-fuses, which can lead to variations in the voltage established at the trip node 124 during a READ operation. Similarly, the temperature of the inverter 126 can affect the input voltage at which the inverter output changes state. Also, the operation of the sense circuit of PMOS and NMOS transistors can vary due to process fabrication and operating voltage, and operating temperature (commonly called “PVT” variation).
E-fuse elements are particularly useful due to their simplicity, low manufacturing cost, and easy integration into CMOS ICs using conventional CMOS fabrication techniques. However, an incorrect READ operation can result in data errors, and accurate reading of E-fuses is critical. It is desirable to provide E-fuse reading techniques that are more accurate compared to those of the prior art.